Xin Dongxi reported on December 16th that at IEDM 2024 (2024 IEEE International Electron Devices Meeting), Intel Foundry showcased several technological breakthroughs including advanced packaging, transistor miniaturization, and interconnect scaling to help drive the semiconductor industry’s development in the next decade and beyond. Intel has increased the throughput in chip packaging by up to 100 times by improving packaging technology, explored solutions to foreseeable interconnect scaling limitations of transistors using copper materials when developing future process nodes, and continues to define and plan the transistor roadmap for advanced gate-all-around (GAA) transistors and other related technologies.
These technological advances come from Intel Foundry’s technology research team responsible for researching and developing breakthrough processes and packaging technologies. Some papers presented at IEDM 2024 were jointly completed by Intel Foundry and other teams. As the industry moves towards the goal of achieving one trillion transistors on a single chip by 2030, technological breakthroughs such as advanced packaging, transistor miniaturization, and interconnect miniaturization are crucial for meeting the future needs of computing applications with higher performance, higher energy efficiency, and higher cost-effectiveness. First, advanced packaging: A new heterogeneous integration solution that increases throughput by up to 100 times. Intel Foundry reported a heterogeneous integration solution for advanced packaging – Selective Layer Transfer (SLT), which can increase the throughput in chip packaging by up to 100 times and achieve ultra-fast chip-to-chip assembly. Compared with traditional chip-to-wafer bonding technology, selective layer transfer can make chips smaller in size and have a higher aspect ratio. The basic idea of this solution is to achieve the flexibility and capability of chip-to-wafer connection with the throughput of wafer-to-wafer connection, enabling the integration of ultra-thin dies with higher flexibility. It also brings higher functional density and can be combined with hybrid bonding or fusion bonding processes to provide a more flexible and cost-effective solution for packaging dies from different wafers. This provides a more efficient and flexible architecture for AI applications. The corresponding technical paper is titled ‘Selective Layer Transfer: An Industry-Leading Heterogeneous Integration Technology’, and the authors include Adel Elsherbini, Tushar Talukdar, Thomas Sounart, and others.2. Transistor Miniaturization: Continuously shortening the gate length and exploring new materials to replace silicon transistor technology. Progress has always been one of Intel’s main businesses. In the most advanced gate-all-around (GAA) transistor field, Intel Foundry has demonstrated silicon-based RibbonFET CMOS (complementary metal oxide semiconductor) technology and the gate oxide module of 2D field-effect transistors (2D FETs) for miniaturization to improve device performance.
To push the miniaturization of RibbonFET GAA transistors to a higher level, Intel Foundry has demonstrated a silicon-based RibbonFET CMOS transistor with a gate length of 6nm and a silicon layer thickness of only 1.7nm. While significantly shortening the gate length and reducing the channel thickness, it has reached the industry-leading level in suppressing short-channel effects and performance. Intel Foundry is researching a gradual development step to replace the channel material from traditional materials to other materials, such as 2D materials. They judge that once the silicon-based channel performance is pushed to the limit, GAA transistors using 2D materials are likely to become a reasonable direction for the next step of development. To further accelerate GAA technological innovation beyond CFET (complementary field-effect transistor), Intel Foundry has demonstrated its research on the manufacturing of 2D GAA NMOS (N-type metal oxide semiconductor) and PMOS (P-type metal oxide semiconductor) transistors, focusing on the research and development of the gate oxide module and miniaturizing the gate length of transistors to 30nm. This research also reports on the industry’s research progress in the field of 2D TMD (transition metal dichalcogenide) semiconductors. Such materials are expected to become a substitute for silicon in advanced transistor processes in the future. GaN is an emerging material for power devices and radio frequency (RF) devices. Compared with silicon, it has stronger performance and can withstand higher voltages and temperatures. The Intel Foundry team found that in the data center field, silicon materials are almost reaching the limit in power transmission, and other material systems represented by 300mm GaN (gallium nitride) are attractive alternative choices. On a 300mm GaN-on-TRSOI (trap-rich silicon-on-insulator) substrate, Intel Foundry has manufactured industry-leading high-performance miniaturized enhanced GaN MOSHEMT (metal oxide semiconductor high electron mobility transistor). Substrates with relatively advanced processes such as GaN-on-TRSOI can bring stronger performance to applications such as power devices and radio frequency devices by reducing signal loss, improving signal linearity and advanced integration schemes based on backside processing of the substrate.III. Interconnect Scaling: Improving the internal interconnects of chips, with a maximum reduction of 25% in inter-line capacitance. The era of copper interconnects is nearing its end. As line widths continue to shrink, the resistivity of copper wires increases exponentially, reaching unacceptable levels. While transistor sizes are shrinking, making them denser and more powerful, there is a lack of wiring needed to connect all these transistors.
One breakthrough method is the subtractive Ruthenium interconnect technology. When the spacing is less than or equal to 25nm, the air gap achieved by using subtractive Ruthenium interconnect technology can reduce inter-line capacitance by up to 25%, which helps to improve chip interconnects and enhance chip performance. Specifically, subtractive Ruthenium interconnect technology uses Ruthenium, a new, key, alternative metallization material, leveraging thin film resistivity and air gaps, to achieve significant progress in interconnect miniaturization. Intel Foundry has pioneered a viable, manufacturable, and cost-effective subtractive Ruthenium interconnect technology on R&D test equipment. This process introduces air gaps without the need for expensive lithographic air gap exclusion zones around vias or the use of self-aligned vias with selective etching. This indicates the advantage of this technology as a metallization solution, replacing the copper damascene process in closely spaced layers. This solution is expected to be applied in Intel Foundry’s future process nodes, or it may explore a reasonable next-generation interconnect technology, compatible with the next generation of transistors and packaging technologies. The corresponding technical paper is titled ‘Subtractive Ruthenium Interconnect Technology Utilizing Air Gaps’, authored by Ananya Dutta, Askhit Peer, and Christopher Jezewski. Conclusion: Three Key Innovations Driving AI Toward Higher Energy Efficiency At IEDM2024, Intel Foundry also shared its vision for the future development of advanced packaging and transistor scaling technologies. The following three key innovation focuses will help AI to develop in a more energy-efficient direction over the next decade: 1. Advanced memory integration to eliminate bottlenecks in capacity, bandwidth, and latency; 2. Hybrid bonding for optimizing interconnect bandwidth; 3. Modular systems and corresponding connection solutions.The exploration of new materials is essential to further enhance Intel Foundry’s PowerVia backside power delivery technology, which plays a crucial role in alleviating interconnect bottlenecks and enabling further transistor scaling. This is vital for the continuous advancement of Moore’s Law and driving semiconductor innovation in the AI era.
Intel Foundry has issued a call to action for the development of critical and breakthrough innovations, continuously advancing transistor scaling and propelling the realization of the ‘trillion-transistor era.’ Intel Foundry outlines the benefits of transistors that can operate at ultra-low voltages (below 300 millivolts) in addressing the increasingly severe thermal bottlenecks and significantly improving power consumption and heat dissipation. The team believes that one of the ways to tackle energy challenges is by employing high-quality transistors with extremely low supply voltages. It’s not just about fabricating one such transistor in a research environment but manufacturing trillions of these transistors with high performance, stability, repeatability, and reliability, enabling their use in product manufacturing.
